1. Technical Field
The present disclosure relates to synchronization techniques.
One or more embodiments may find application in integrated circuits.
2. Description of the Related Art
In the sector of integrated circuits (ICs) the requirement of supplying signals at high frequency synchronized in an accurate way is increasingly felt.
With the continuous rise in clock frequencies, it becomes ever more problematical to maintain accurately the characteristics of a timing signal at a given frequency with respect to any possible skew linked to process, voltage, and temperature (PVT) variations. The behavior in regard to process, voltage, and temperature may vary from one device to the next, with certain tolerances, and these variations may change the value of the delay. These factors can also induce negative effects in terms of jitter.
High-speed synchronous integrated circuits, such as, for example, microprocessors and memories, can function accurately in the presence of clock signals aligned in a precise way. With the continuous rise in clock frequencies and in the number of components (e.g., transistors) there is felt to an increasingly stringent extent the need to provide synchronization systems that are able to reduce and, at least virtually, eliminate any possible skew and undesirable jitter phenomena linked to the aforesaid process, voltage, and temperature (PVT) variations.
If reference is made to high-voltage (HV) devices, there is felt to an increasing extent the need to provide high-frequency signals synchronized in an accurate way, the purpose of this being, for example, to reduce power absorption and improve performance of the systems that use such circuits, for instance, DC/DC converters, electromedical devices, etc. In particular, with the continuous increase of resolution in high-voltage synchronization systems, the time error produced by the integrated circuits may contribute significantly to the overall time error.
Application of solutions of this nature to contexts in which higher voltage signals are present comes up against critical aspects of various nature. For instance, in printed-circuit boards (PCBs) on which high-voltage signals are present it is possible to find high levels of crosstalk, which are particularly critical in the case where an integrated component operating in this context is arranged to perform functions timed, for example, with reference to pulsed signals, for instance, pulsed signals with variable duty cycle such as PWM signals.
The picture appears even more critical in the case where a number of high-voltage signals are present of which it is desired to achieve a high level of mutual synchronization.
Aspects of this nature have already been tackled by resorting to open-loop or closed-loop synchronization topologies that are able to operate, for example, in a CMOS technology context.
For instance, various implementations can operate with phase-locked loops (PLLs) or with (digital) delay-locked loops (DLLs), which are suited to being calibrated in regard to the PVT factors. There are, however, possible disadvantages in terms of consumption and, in addition or in the alternative, occupation of circuit area and limitations to just the variations of phase of the clock signal.
In particular, in addition to having a limited band, these locked loops can supply a signal having a resolution directly proportional to the input frequency. A variable clock frequency can lead to long delay steps when the frequency is low. Any technological limitation in terms of speed may be such as to limit the upper frequency that can be used.